In a semiconductor memory device, input circuits such as a data-in buffer circuit and an address buffer circuit are provided. An address pin is connected to the input node of the address buffer circuit and a data pin is connected to the input node of the data-in buffer circuit, and an address and data are input to them. These input circuits detect the "High" or "Low" or "1" or "0" of data by comparing an externally input voltage (which is hereinafter simply referred to as Vin) which is data of TTL level with a reference potential (which is hereinafter simply referred to as Vref) and amplifies and converts the detected signal to a signal of MOS level used inside the memory device.
FIG. 1 is an equivalent circuit diagram of the above address buffer circuit. The address buffer circuit is constructed to include p-channel MOS transistors Q1 and Q2, n-channel MOS transistors Q3 to Q10, and MOS capacitors C1 and C2. The operation of the circuit is controlled by internal control signals .phi.1, .phi.2 and .phi.3 which are created based on a control signal (CAS, RAS or the like in a DRAM) input from the exterior and the circuit responds to the internal control signals at respective timings to latch the input address. Then, whether Vin is "High" or "Low" is detected according to whether the potential of Vin is higher than Vref or not and it is output as address signals Aout and Aout.
Vref is a potential used as a reference in the circuit operation of the semiconductor memory device and is created in the memory device. Vref is normally set at a positive potential and it is particularly important in the circuit operation to prevent variation in the potential.
In a semiconductor memory device having the above-described input circuit, a test for checking the operation characteristic of the semiconductor memory device is effected by adding a negative potential (for example, approximately -2.0 V) to Vin, but in this test, the following problems occur.
The problem is explained with reference to FIG. 2. FIG. 2 provides a view of the structural arrangement of a portion of a semiconductor memory device in which the n-channel MOS transistors Q3 to Q10 and MOS capacitors C1 and C2 of the address buffer circuit shown in FIG. 1 are formed.
A p-well region 26 is formed in the main surface area of an n-type semiconductor substrate 21. n.sup.+ -type impurity diffused layers 22 and 23 and a p.sup.+ -type impurity diffused layer 28 are separately formed in the surface area of the p-well region 26. The impurity diffused layer 22 serves as a drain region of the MOS transistor Q9 and Vin is applied to the diffused layer 22 via a wiring 24. The impurity diffused layer 23 serves as a drain region of the MOS transistor Q10 and Vref is applied to the diffused layer 23 via a wiring 25. A ground potential (which is hereinafter simply referred to as Vss) is applied to the impurity diffused layer 28 via a wiring 27. As a result, the ground potential is applied to the p-well region 26.
Although not shown in the drawing, the source regions of the n-channel MOS transistors Q9 and Q10, the source and drain regions of the n-channel MOS transistors Q3 to Q8, the MOS capacitors C1 and C2 and the like are formed in the p-well region 26. The p-channel MOS transistors Q1 and Q2 are formed in the main surface area of the substrate 21.
With the above substrate structure, when a function test is effected by applying a negative potential to the above-described input pin, in other words, when Vin is a negative potential, minority carriers are generated in a junction between the impurity diffused layer 22 and the p-well region 26. As shown by the potential energy diagram in FIG. 3, part of the minority carriers flows into the n-type semiconductor substrate 21 but the remaining minority carriers which have lost their way flow into the impurity diffused layer 23 so that Vref may be lowered. Since Vref is a potential used as a reference in the circuit operation, the semiconductor memory device may be erroneously operated if the potential has varied.
Thus, in the semiconductor device formed in the n-type semiconductor substrate, an erroneous operation caused by variation in the substrate potential due to injection of the minority carriers develops into a serious problem.
Accordingly, an object of this invention is to provide the substrate structure of a semiconductor device capable of eliminating the above-described conventional defects and enhancing the reliability.